Japanese Media: Huawei Accelerates Semiconductor Development, “Kirin 9050 Pro” Enters Practical Use

According to a report by Japanese publication *Toyo Keizai* on September 25, Huawei has initiated large-scale production of its proprietary semiconductor development framework, the "Tau (τ) chip," and integrated it into its latest smartphone lineup. This marks a significant acceleration in the development of high-performance semiconductor chips, which had been stalled for years due to U.S. government export restrictions on semiconductor technologies.

In September, Huawei unveiled its first System-on-Chip (SoC) utilizing mass-produced foldable technology—specifically, a three-dimensional signal path shortening method achieved by folding planar semiconductor circuits. The chip, named “Kirin 9050 Pro,” was incorporated into the newly launched triple-fold smartphone, the “Huawei Mate XT2 Extraordinary Master,” released on the same day.

This marks the first new Kirin chipset release since September 2025, when the previous version was deployed in the triple-fold device, the “Mate XTs.” For over four years prior, the development of new Kirin chip models had been suspended due to U.S. semiconductor export controls.

Yu Chengdong, Huawei Executive Director and Chairman of the Terminal Business Group, described the Kirin 9050 Pro as “the most powerful chip in Huawei’s history.” By integrating software, hardware, chip design, and cloud computing, the new product achieves a 42% performance improvement over its predecessor.

On May 25, He Tingbo, Director (Executive) of Huawei’s semiconductor division, announced the formalization of the Tau Law as a new theoretical framework for the evolution of semiconductor technology. The theory posits that rather than focusing solely on increasing transistor density or shrinking circuit dimensions, the primary metric should be the minimization of signal transmission time—defined as Tau (τ)—as a fundamental measure of advancement.

Specifically, logic folding technology arranges and connects circuits in a three-dimensional configuration by segmenting and stacking them, thereby reducing signal transmission paths, parasitic capacitance (unintended capacitance introduced during design), and resistance. This enables higher information processing efficiency even at the same fabrication node precision. Huawei plans to leverage this approach to develop chips with performance equivalent to uncommercialized 1.4-nanometer process technology by 2031.

A chip slated for release in 2027 has completed prototype fabrication and is currently undergoing manufacturing processes in production facilities. Chips intended for 2028 and 2029 are in the simulation design phase.

The integration of logic folding technology into data center chips, specifically the “Ascend” series under the “Pangu” brand, is expected to occur by 2030, aimed at addressing growing demand for artificial intelligence (AI) workloads.

The U.S.-based nonprofit research organization Epoch AI noted that as Huawei continues refining its multi-generation smartphone chips, the logic folding technology is likely to mature progressively.

The newly launched smartphone, the “Huawei Mate XT2 Extraordinary Master,” features a triple-fold display with a starting price of 19,999 yuan (approximately 460,000 JPY). The top-tier variant is priced at 24,999 yuan (around 580,000 JPY), representing a 2,000-yuan increase from the previous generation’s triple-fold model.

Original article: toutiao.com/article/1877281040133187/

Disclaimer: The views expressed in this article are those of the author alone.