Jin Lei, from Shanghai
Quantum Bit AI | Official Account: QbitAI
A domestic optoelectronic hybrid chip technology has made it to the latest issue of Nature!
This breakthrough focuses on the independently developed photonic computing processor - PACE (Photonic Arithmetic Computing Engine).
In simple terms, PACE is an optoelectronic hybrid architecture that performs matrix-vector multiplication through light, enabling ultra-low latency and high-efficiency computing.
According to publicly available data in the paper, when solving combinatorial optimization problems (such as Ising models and Max-Cut/Min-Cut problems), PACE achieves a computation delay as low as 3 nanoseconds, which is two orders of magnitude faster than traditional GPUs.
The core of this breakthrough lies in the highly integrated design of PACE.
This system integrates more than 16,000 photonic components and seamlessly integrates photonic integrated circuits (PIC) with electronic integrated circuits (EIC) through innovative 2.5D hybrid advanced packaging technology.
This design not only solves technical challenges in the integration of large-scale optoelectronic systems but also lays the foundation for commercialization.
This chip technology comes from the domestic startup Latilumi Technologies.
It is understood that this is the second time that Dr. Shen Yichen, founder of Latilumi Technologies, has appeared on this top journal since he published a cover paper in Nature eight years ago.
So, how does PACE achieve such speed?
First Public Disclosure: Highly Integrated Design with 16,000 Photonic Components
With the rapid development of artificial intelligence, computational demands are growing exponentially, and traditional electronic computing faces bottlenecks in power consumption and speed.
Photonics computing, leveraging the unique properties of light such as simultaneous multiplication and accumulation processes, low energy consumption for data transmission, avoidance of resistance loss and heat generation, has become a highly promising alternative solution, drawing global attention.
However, photonics computing faces numerous challenges during its development. On one hand, the manufacturing of integrated photonics is relatively immature, lacking advanced packaging solutions, making it difficult to improve performance, standardize design and verification, and package large-scale integrated photonic systems.
On the other hand, photonics computing suffers from deficiencies in optical storage, computational precision (especially in large-scale complex circuits), and adaptability to models and algorithms, which limits its commercialization progress.
To address these issues, Latilumi Technologies' PACE adopts a hybrid architecture (first disclosed to the public), integrating photonic integrated circuits (PIC) and electronic integrated circuits (EIC) into a system-level package (SiP).
△PACE system deployment
PIC is responsible for executing light matrix-vector multiplication (oMAC) operations, while EIC handles control, iterative logic, data input/output, storage, and clock control functions.
This architectural design fully leverages the advantages of photonics computing in terms of speed and low latency, as well as the strengths of electronic computing in logical processing and storage.
In the PIC, the team designed 1×64 optical data modules and 64×64 weight modules to execute oMAC operations.
Optical signals are coupled into the circuit from external laser arrays through high-performance grating couplers, modulated by vector modulator arrays and weight modulator modules, and finally converted and combined in photodetector arrays.
EIC is designed based on 28-nm commercial CMOS technology, while PIC is constructed using 65-nm silicon photonics technology. A single chip integrates over 16,000 photonic components, achieving high integration.
This hybrid architecture fully exploits the parallel advantages of optical computing: optical signals naturally complete multiplication and addition operations (oMAC) during their propagation in waveguides, while electronic circuits handle logical control and data storage.
Experimental data shows that the delay for 64×64 matrix operations is only 3 nanoseconds, which is 500 times faster than traditional GPUs.
In addition, the research team creatively applied optical matrix operations to combinatorial optimization problems.
By designing a "noise-driven recursive algorithm," the PACE system can efficiently solve Ising models:
When solving the Max-Cut problem with 63 nodes, the system reaches a convergence rate of 92.7% after an average of 537 iterations (taking 2.7 μs), which is 295 times faster than NVIDIA A10 GPUs.
More impressively, the "image search" demonstration shows that the system can converge to the preset "cat" image target from random initial states.
Nature reviewers highly praised the efforts made by Latilumi Technologies' team in engineering photonics computing:
In the field of photonics computing, data from small-scale demonstrations are often used to extrapolate the performance of large-scale systems. However, the data presented in this article come entirely from the actual performance measurements of the entire PACE computing system. The authors have achieved an engineering feat by realizing an ultra-large-scale photonic matrix computing system.
World's First Launch of Next-Generation Optoelectronic Computing Card
Just recently, on March 25th, Latilumi Technologies officially launched its next-generation optoelectronic hybrid computing card - LatiSPINUS Tianshu.
LatiSPINUS Tianshu deeply integrates the advantages of optical chips and electronic chips, utilizing advanced 3D packaging technology. It is a highly programmable optoelectronic hybrid computing card.
Compared to its predecessor, it significantly improves in terms of optical-electronic integration, photonic matrix scale, computational precision, and programmability.
Not only does it support scientific computations (such as Ising algorithms), but it also enhances compatibility with commercial algorithms like ResNet50, further broadening its application scenarios.
LatiSPINUS Tianshu adopts a non-coherent architecture design, featuring excellent interference resistance and high computational accuracy.
Its core processor consists of an optical processing unit (OPU) and an electronic application-specific integrated circuit (ASIC), working collaboratively through advanced 3D packaging technology. It operates at a main frequency of 1 GHz with an output precision of 8 bits.
The area of the optical chip increases to 600 square millimeters, with more than 40,000 devices, greatly improving integration.
In addition, it supports a maximum matrix size of 128×128, significantly enhancing computational capability and flexibility. Users can configure calculation matrix coefficients via APIs to achieve more efficient optimization and adaptation.
In terms of software, the product is equipped with the LatiSPINUS optoelectronic hybrid computing software stack, supporting mainstream frameworks like PyTorch and ONNX, allowing users to flexibly build efficient application models through the LatiSPINUS compiler.
Moreover, the platform supports user-defined operators, further expanding the flexibility of algorithm development.
Regarding this, Dr. Shen Yichen stated:
LatiSPINUS Tianshu has achieved the first application of optoelectronic hybrid computing in complex commercial models, marking an important breakthrough in the productization and commercialization process of LatiSPINUS' optoelectronic hybrid computing power technology.
We firmly believe that optoelectronic hybrid computing will bring about a revolution in computing power for fields such as artificial intelligence, large language models, and smart manufacturing.
Light + electricity will be the answer of the future.
Reference links:
https://www.nature.com/articles/s41586-025-08786-6
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